Current Tunnelling in MOS Devices withAl 2 O 3 /SiO 2 Gate Dielectric

Abstract

With the continued scaling of the SiO 2 thickness below 2 nm in CMOS devices, a large direct‐tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al 2 O 3 has emerged as one of the most promising high‐k candidates in terms of its chemical and thermal stability as its high‐barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al 2 O 3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al 2 O 3 /SiO 2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al 2 O 3 /SiO 2 interface is also discussed.