SASCr3: A real time hardware coprocessor for stereo correspondence

Abstract

Main focus of this paper is to show the relevant improvements for a real time hardware co-processor for Stereo-Matching. The approach follows the well-known scheme for strings alignment proposed by Needleman&Wunsch, commonly used in bio-informatics. The principal improvement concerns the algorithm parallelization in FPGA design, in an hardware architecture many resources can work at the same time avoiding the reduction of system performance. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. For many parallelism degrees the synthesis and performance results are shown, for this purpose a Lattice ECP3-70 is set as target device. The aim of this project is to build stereo vision system for embedded application, charaterized by low power usage and device cost. The actual circuit is an updated version of SASCr2 design. Performance is benchmarked against the former implementation.