Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs

Abstract

An energy-efficient capacitor-splitting digital-to-analogue converter (DAC) scheme with high-accuracy for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed method uses a split-capacitive-array DAC structure and optimises the switching energy during conversion using energyefficient 'up' transition. The proposed switching scheme achieves a 96.91% switching energy reduction and a 75% area reduction compared with the conventional method. In addition, the third reference voltage (Vcm) has no effect on the accuracy of the SAR ADC except the least significant bit, resulting in a good trade-off between the energy-efficiency and accuracy of the ADC.