FPGA Based Transient Fault Generate and Fault Tolerant for Asynchronous and Synchronous Circuits

Abstract

In recent years, it is a challenging task to design and test VLSI circuits because of its complexity. The manufacturing of the digital integrated circuits with defects, affects the productivity and reliability of the system. If the defects are more in the systems, then it results faults. To resolve the faults in digital circuits, an active fault tolerant system is required. In this paper, efficient hardware architecture of transient fault injection and tolerant system (TFI-FTS) for synchronous and asynchronous circuits is designed. The TFI system is designed using Berlekamp Massey Algorithm (BMA) based Linear-feedback Shift Register (LFSR) with fault logic and one-hot encoder followed by data register. The FTS is designed using Triple modular redundancy (TMR) with majority logic. The asynchronous and synchronous circuits are considered from the 74X-Series and ISCAS’89 benchmark circuits respectively. The overall work is synthesized and implemented on prototyped FPGA-Artix-7. The fault coverage is analyzed with the simulation environment on Modelsim simulator.