TSU: A Two-stage update approach for persistent skiplist

Abstract

Skiplist, a widely used in-memory index structure, could incur crash inconsistency when running on emerging NVRAM (Non-Volatile Random Access Memory). Logging or strict serialization can ensure crash consistency at the cost of severe performance degradation. In this paper, we propose TSU, a Two-stage update approach to improve the performance of persistent skiplist while preserve crash consistency. TSU exploits space locality of skiplist and atomic write of NVRAM, thus effectively reducing expensive cache line flush (clflush) operations. To this end, we category all four crash inconsistent states into two types: recoverable and unrecoverable. TSU could guarantee the crash state is recoverable by constraining the memory access order for insertion and deletion. We further design a persistency algorithm to reduce clflush by preserving the memory persistent order of skiplist update. In addition, we develop a concurrent search for TSU. The evaluation result shows that TSU can reduce cache line flush with up to 47.6%, and decrease the average request latency by up to 36% for insertions compared to the strict serialization.