Design of an area-efficient FinFET-based approximate multiplier in 32-nm technology for low-power application

Abstract

For applications, where the performance and accuracy are less important inexact computing can be used. The power efficiency increases as the bit-based multiplication is not done for full word length. Applications where speed and power are dominant compared to accuracy inexact multipliers are the first choice. In this approach, the partial products of the approximate multiplier are changed. Two variants of multipliers are designed. One is with CMOS and other with FinFET. The proposed FinFET-based multiplier circuit reduces the leakage current which ultimately results in the power consumption reduction. The proposed compressor-based multiplier reduces the number of operands and partial products. The inexact computing reduces the number of interconnects and components. The proposed multiplier circuits are compared with the existing counterparts and found that the performance improvement is 40.61%. In future, a FinFET-based Multiply-Accumulate unit (MAC) for biomedical application will be proposed.