Effective FPGA-based enhancement of quantitative frequent itemset mining

Abstract

Frequent itemset mining (FIM) algorithms are widely used to discover common patterns in large-scale data sets. In conventional CPU-based systems, mining algorithms, which are usually data and memory intensive, often lead to critical power and latency issues growing even worse with a larger scale of data sets. Having identified the pipelining workflow behind the logic of frequent itemset mining, we propose a quantitative mining algorithm named Q-Bit-AssoRule and further design a pipelined FPGA-based implementation of Q-Bit-AssoRule algorithm to accelerate frequent itemset mining processing, achieving better performance, throughput, scalability as well as less hardware cost. Our evaluation result shows that our implementation outperforms other hardware approaches in terms of clock frequency and throughput.