Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to parameter variations is demonstrated for four different register designs. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is determined. © Springer-Verlag Berlin Heidelberg 2005.
CITATION STYLE
Roberts, W. R., & Velenis, D. (2005). Parameter variation effects on timing characteristics of high performance clocked registers. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3728 LNCS, pp. 508–517). Springer Verlag. https://doi.org/10.1007/11556930_52
Mendeley helps you to discover research relevant for your work.