This paper proposes a cost-effective VLSI architecture to improve the three-step search (TSS) algorithm for efficient motion estimation. A weighted SAD is defined as the new distortion measure instead of SAD for motion vector selection to remedy the fault of the TSS algorithm. The proposed TSS architecture is superior to conventional TSS architecture in terms of coding performance. Moreover, the additional hardware implementation cost of the proposed architecture is relatively negligible. The proposed architecture achieves best tradeoff in terms of speed and hardware cost. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Yin, H. B., Xia, Z. L., & Lou, X. Z. (2007). An improved three-step hierarchical motion estimation algorithm and its cost-effective VLSI architecture. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4810 LNCS, pp. 822–830). Springer Verlag. https://doi.org/10.1007/978-3-540-77255-2_98
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