A parallel permutation multiplier for a PGM crypto-chip

Abstract

A symmetric key cryptosysteni, called PGM, based on log- arithmic signatures for finite permutation groups was invented by S. Magliveras in the late 1970's. PGM is intended to be used in cryptosystems with high data rates. This requires exploitation of the potential parallelism in composition of permutations. As a first step towards a full VLSI implementation, a parallel multiplier has been designed and implemented on an FPGA (Field Programmable Gate Array) chip. The chip works as a co-processor in a DSP system. This paper explains the principles of the architecture, reports about implementation details and concludes by giving an estimate of the expected performance in VLSI.