Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder

Abstract

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposedtriple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. Byincorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, themodelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained throughXOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder,only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designedwith cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reportedwork and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed.The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOSdesigns.