Sizing the Intrinsic Gain Stage

0Citations
Citations of this article
6Readers
Mendeley users who have this article in their library.
Get full text

Abstract

Sizing methods assessing drain currents and gate widths of a simple circuit are reviewed in this chapter. The circuit, shown in Fig. 1.1, consists of a saturated common source transistor loaded by a capacitor. A constant current source is feeding the drain. The circuit is called currently the ‘Intrinsic Gain Stage’ (I.G.S.), the name ‘intrinsic’ underlining the fact that few parts aside the transistor control the performances of the circuit. Our objective is to find gate widths and drain currents enabling to achieve a prescribed gain-bandwidth product ωT. We therefore consider the small signal equivalent circuitshown in Fig. 1.2. The input is an open circuit while the output consists of a dependent current source gm vin (where gm represents the transconductance of Q) in parallel with the output conductance gd and the capacitor C.

Cite

CITATION STYLE

APA

Jespers, P. G. A. (2010). Sizing the Intrinsic Gain Stage. In Analog Circuits and Signal Processing (pp. 1–9). Springer. https://doi.org/10.1007/978-0-387-47101-3_1

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free