Efficient high-level coding in a PLC to FPGA translation and implementation flow

Abstract

In the automation industry, PLCs have been the preferred implementation platform for many decades, due to their reliability, robustness and flexibility characteristics. However, the advances of the electronics industry have always kept automation engineers busy, looking for alternative platforms, proposed for the most demanding applications. Recently, the introduction of powerful and energy efficient FPGA devices has turned their interest towards methodologies to implement PLC applications with FPGAs, in automated or semiautomated ways. This paper evaluates such a methodology, which involves a fresh and productivity boosting technology, C-based FPGA programming. As FPGAs have made hardware designs wider accepted (compared to ASICs), C-based FPGA programming promises to make them even wider accepted (compared to HDL programming), provided specific, hardware related C-level coding guidelines are followed, that can greatly improve quality of results. The proposed methodology in this paper starts form low level PLC code (IL/STL) and after a disassembly-like phase, generates C code ready for FPGA programming. Through experimentation with demanding applications that involve floating point calculations, it is shown that when proper C-level coding guidelines are followed, performance gains (faster hardware) of up to 90% can be achieved.