Effect of interface roughness on gate bias instability of polycrystalline silicon thin-film transistors

Abstract

The effect of the SiO 2/polycrystalline silicon (polysilicon) interface roughness on the stability of n-channel large grain polysilicon thin-film transistors (TFTs) is investigated. The positive gate voltage of 20 V is used in the bias stress experiments, with the source and drain grounded. It is shown that the current through the gate oxide and the stability of the TFT are directly related to the importance of the interface roughness. The evolution of the TFT parameters with stress duration indicates that the turn-on voltage V on and the subthreshold swing voltage S are degraded due to the generation of dangling bond midgap states, while the leakage current I L and the maximum transconductance G m are degraded due to the generation of strain-bond tail states. Moreover, the parameters V on and I L are found to degrade faster than the parameters S and G m, respectively, due to electron trapping in the gate oxide. © 2002 American Institute of Physics.