Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

Abstract

Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying gm/ID-based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layout-dependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk (cdb) and source-to-bulk (csb) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.