Block Rearrangements and TSVs for a Standard Cell 3D IC Placement

Abstract

The block rearrangements for vertically stacked integrated circuits (ICs) are done moving the blocks as per the cost function which in return will reduce the overall wire length and allocate white spaces for a standard cell benchmark circuit. This white space allocation will be the most adaptable way for routability when the multiple layers in 3D IC are designed. In this paper, the 3D IC has three layers which are vertically stacked, and through-silicon vias (TSVs) are placed in between the layers for interconnection between the block and also between the layers. Moreover, the thermal level of a TSV is computed using COMSOL Multiphysics. As a result, the wire length between the layers is optimized to 8% using JAVA background, and thermal level is computed as 10%. The input is taken as IBM-PLACE benchmark circuits.