Efficient power-sum systolic architectures for public-key cryptosystems in GF(2m)

Abstract

The current paper presents a new algorithm and two architectures for the power-sum operation (AB2 + C) over GF(2m) using a standard basis. The proposed algorithm is based on the MSB-first scheme and the proposed architectures have a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed parallel-in parallel-out array are about 19.8% and 25% lower, respectively, than Wei’s. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inverse/division architecture.