Abstract
This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.
Cite
CITATION STYLE
Tiri, K., & Verbauwhede, I. (2004). Secure logic synthesis. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3203, pp. 1052–1056). Springer Verlag. https://doi.org/10.1007/978-3-540-30117-2_125
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