Efficient DVFS to prevent hard faults for many-core architectures

Abstract

Dynamic Voltage and Frequency Scaling (DVFS) is a widely-used and efficient technology for Dynamic Power management (DPM). To avoid hard faults caused by voltage and frequency scaling, some overhead always be imposed on the performance of applications due to the latency of DVFS. Besides, on many-core architectures, the design of multiple voltage domains has made the latency of DVFS a much more significant issue. In this paper, we propose an efficient DVFS scheme to prevent hard faults, meanwhile eliminating the impact of latency of DVFS as possible. The main idea is applying Retroactive Frequency Scaling (RFS) where the latency of DVFS might be introduced. Based on the analysis, our approach is expected to achieve noticeable performance improvement on many-core architectures. © 2014 IFIP International Federation for Information Processing.