Abstract
In this paper, we focus on engineering Pareto -optimal digital circuits given the expected input/output behaviour with a minimal design effort. The design objectives to be minimised are: hardware area, response time and power consumption. We do so using the Strength Pareto Evolutionary Algorithms. The performance and the quality of the circuit evolved for some benchmarks are presented then compared to those of single objective genetic algorithms as well as to the circuits obtained by human designers. © Springer-Verlag Berlin Heidelberg 2005.
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CITATION STYLE
Nedjah, N., & De Mourelle, L. M. (2005). Pareto-optimal hardware for digital circuits using SPEA. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3533 LNAI, pp. 534–543). Springer Verlag. https://doi.org/10.1007/11504894_72
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