Design and Evaluation of Adiabatic Arithmetic Units

Abstract

Adiabatic design is an attractive approach to reducing energy consumption in VLSI circuits after exhausting the potential of conventional energy-saving techniques. Despite the plethora of adiabatic logic architectures that have been proposed in recent years, several practical considerations in the design of nontrivial adiabatic circuits remain largely unexplored. Moreover, it is still unclear whether adiabatic circuits of significant size and complexity can achieve substantial savings in energy dissipation over corresponding conventional designs. We recently designed several low-power arithmetic units using a dual-rail adiabatic logic design style. We also designed static CMOS versions of these units and compared their energy dissipation with their corresponding adiabatic designs. In this paper we describe our implementations, discuss architecture and logic-level issues related to our adiabatic designs, and present the findings of our empirical comparison. Our results suggest that adiabatic logic can be used for the implementation of relatively complex VLSI circuits that dissipate significantly less energy than their corresponding CMOS designs.