Optimality of gauge and degree-sensitive VLSI layouts of planar graphs

Abstract

It is known that the layout area of a planar graph is influenced most by input parameters such as the size of its nodes, and its resemblance to an outerplanar graph. The latter is measured by the gauge of the graph. We examine the area-optimality of these layouts by exhibiting gauge and degree sensitive lower bounds on layout area. These results span the spectrum between outerplanar graphs, which have gauge 1, and arbitrary planar graphs, which may have gauge Ω(N), while simultaneously allowing vertices of arbitrarily large degree. In cases where we cannot establish optimality, our bounds place previous results in context by demonstrating gaps between the lower and upper bounds which are sensitive to these parameters. Moreover, we establish matching lower bounds in these cases for corresponding nonplanar graphs having identical partitioning characteristics. Previous gauge and degree sensitive techniques for finding layouts of planar graphs did not consider minimizing the maximum wire length. We address this problem briefly to provide evidence that results similar to layout area can be obtained for this problem as well.