Nanolithography

Abstract

The patterning of devices and circuits on nano-chips continues to be a major challenge in realizing more performance on-chip. Both for physical device reasons and for lithography limits, the roadmap for chip-product nodes has been re-written, so that node names have become quite different from minimum dimensions on-chip. 2018 became the introduction-year for Logic Industry Node “7 nm” with minimum features of 14 nm, and the IRDS Lithography roadmap sees 2030 as the “1.5 nm” industry node with 7 nm minimum features. The work-horse continues to be 193 nm DUV Liquid-Immersion Multi-Printing, with opportunities for Nano-Imprint, Multiple-Electron-Bean Direct Writing and Directed Self-Assembly. To support the major drive towards 3D integration, new patterning and precision-alignment techniques will be introduced (Chaps. 8–11, 13 and 15).