A low power, high speed 18-transitor true single-phase clocking D flip-flop design in 90nm cmos technology

Abstract

In this paper the authors came up with a contemporary low power, high-speed 18-transistor true single-phase clocking D flip-flop (FF) design using complementary pass-transistor logic. This design is a master-slave-type logic structure and hybrid logic design consisting of complementary pass-transistor logic style and static CMOS logic style. In order to reduce the number of transistors and to simplify the circuit complexity complementary pass-transistor logic style is used. In this design state transition is faster in the slave latch which enhances time performance using a virtual VDD technique. The circuit is designed using GPDK 90nm CMOS technology and the simulation results show better performance indices such as average power consumption, clock-to-Q delay, data-to-Q delay, PDP and area of utilization.