Design and FPGA Implementation of a Lifting Scheme 2D DWT Architecture

  • Basheer N
  • Mohammed M
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For multi-level decomposition the same operations mentioned above are performed on the (LL) subband as the input instead of the original image, giving pyramid wavelet transform. II. THE LIFTING SCHEME The Lifting scheme (LS) is a method to simplify performing the wavelet transform in an efficient way. The (LS) has some advantages when compared with classical filter banks method, such as the fewer and simpler arithmetic computations required, the simple and fast hardware implementation, the ease of inverse implementation, occupying less memory storage, in addition, the (LS) is more appropriate for high speed and low power applications such as the image/video processing applications. The disadvantages of lifting scheme that the multiplier and adder delays are longer than convolution ones (has longer critical paths) [3]. The (LS) can be performed by three steps: the split stage, the predict stage, and the update stage. In the split stage the input signal or image is separated into even and odd indexed samples. The predict stage computes the high pass filter coefficients representing the details subband. The update stage gives low pass filter coefficients which stands for the approximation subband of the DWT process. For (5/3) wavelet filter the predict and update stages are represented in following equations [4]: D[2n+1] = X[2n+1]-0.5(X[2n] + X[2n+2]) (1) A[2n] = X[2n] + 0.25(D[2n-1] + D[2n+1] (2) Where: X[n]: is the input signal. D[2n+1]: the details coefficients. A[2n]: the approximations coefficients. From lifting scheme wavelet transform equations, it is noticed that hardware design requires only adders and shifters instead of multipliers. Fig. 2 shows the lifting scheme 2-D DWT block diagram. Fig 2. Block diagram for the two dimensional FDWT using lifting scheme. III. PROPOSED ARCHITECTURE FOR DWT This section presents and explains the overall design of a 2-D DWT module, hardware and software tools that are used for design simulation, implementation, and the output results verification. The following sections explain the main design steps, starting with word length, data type representation for hardware design, simulation and testing the results with MATLAB program. After that, the VHDL design used for DWT processor unit, arranging the on-chip internal memory units, and control unit are given. The chip scope program is used as a verification tool for checking and testing the application results. A. Data Representation And Word Length: At first, before designing the 2-D DWT processor, data type representation and image pixels word length must be taken into consideration. There are two ways for data representation with hardware design, either floating point or fixed point. By representing data in floating point method the results will be more accurate due to the greater range of numbers (32 bits or 64 bits), but this accuracy requires more silicon area on FPGA and needs more complex design [10]. Fixed point representation has the advantages of less silicon area on FPGA, and easier to implement a design [10]. So the fixed point method is used to represent the data. The most common representation for fixed point numbers is the 2΄s complement, this type is appropriate with hardware design for arithmetic computations [10]. Another important consideration is the word length, which means, the number of bits per pixel. The original image data word length is 8-bits per pixel, this amount of bits is not enough for wavelet transform coefficients. It is observed that the retrieved image in inverse discrete wavelet transform has distortion, because of overflow condition. The overflow occurs when the addition operation result may be larger than can be held in the word length being used. In DWT the word length of wavelet coefficients will grow gradually in FDWT in each DWT level, and as the DWT levels are more. To select the appropriate word length, the MATLAB program is used for writing appropriate code to simulate the (5/3) wavelet filter in (FDWT) and (IDWT). With (FDWT) MATLAB program the cameraman picture of size (256×256×8) is used as original input image, it is analyzed for three levels of decomposition by using different word lengths, then the (IDWT) is used to reconstruct the retrieved image from the third level, as shown in the Fig. 3. Where, (a) original image, (b) one decomposition level, (c) two decomposition levels, and (d) three decomposition levels. Fig 3. FDWT for three decomposition levels.




Basheer, N. M., & Mohammed, M. M. (2014). Design and FPGA Implementation of a Lifting Scheme 2D DWT Architecture. International Journal of Recent Technology and Engineering, 2(1), 34–38. Retrieved from

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