Automatic temporal floorplanning with guaranteed solution feasibility

Abstract

This paper presents an automatic design synthesis technique for Dynamically Reconfigurable Logic (DRL) systems. Given an input behavioural algorithm, a target technology library server and a set of design constraints, the synthesis algorithm will generate a DRL design solution in a form of a 3D floorplan and a design schedule. The technique optimises the design solution in a multiple-objective design search space, while making realistic assumptions about the implementation reconfiguration overheads. Partial reconfiguration is considered if such a feature is available in the target technology. Simultaneous consideration of the multiple design objectives at various abstraction levels, together with a realistic estimation of the reconfiguration overheads, guarantees the feasibility of the automatically generated solutions. The presented approach is based on generic algorithms with problem-specific coding and operators. The performance of the algorithm was tested using a selection of small benchmarks within the DYNASTY Framework.