Hardware implementation of MFCC feature extraction for speech recognition on FPGA

Van Lan Dao; Van Danh Nguyen; Hai Duong Nguyen; Van Phuc Hoang

Conference Proceedings

Hardware implementation of MFCC feature extraction for speech recognition on FPGA

Dao V
Nguyen V
Nguyen H
et al.

Advances in Intelligent Systems and Computing (2017) 538 AISC 248-254

DOI: 10.1007/978-3-319-49073-1_27

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Abstract

In this paper, an FPGA-based Mel Frequency Cepstral Coefficient (MFCC) IP core for speech recognition is presented. The implementation results on FPGA show that the proposed MFCC core achieves higher resource usage efficiency compared with other designs.

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Dao, V. L., Nguyen, V. D., Nguyen, H. D., & Hoang, V. P. (2017). Hardware implementation of MFCC feature extraction for speech recognition on FPGA. In Advances in Intelligent Systems and Computing (Vol. 538 AISC, pp. 248–254). Springer Verlag. https://doi.org/10.1007/978-3-319-49073-1_27

Hardware implementation of MFCC feature extraction for speech recognition on FPGA

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