A parallel transitive closure computation algorithm for VLSI test generation

Abstract

This paper presents an efficient scalable parallel algorithm for transitive closure computation and its application to solve VLSI test generation problem. The transitive closure computation is the core of the test generation process and it will take huge time, sometimes unaffordable, if it is computed on serial machines for generating patterns for large practical VLSI circuits. The proposed algorithm divides the transitive closure computation into n×n tasks using data parallelism and it takes polylogarithmic time using polynomial number of processors. Load balancing techniques: static and dynamic and performance metrics like speedup, efficiency, scalability and isoefficiency function are taken into account for the algorithm development. The algorithm, so developed, has been implemented in a heterogeneous distributed computing environment using Parallel Virtual Machine (PVM) and successfully tested by generating test patterns for example practical circuits. Experimental results given in the paper show the effectiveness of the proposed algorithm.