NoC router power macro-modeling at high level

Abstract

This paper proposes a methodology for power extraction of the Network-on-Chip router. The router power model is devoted to overcoming the shortcoming of existing architecture-level power simulators with higher accuracy and providing a fast and precise power profile to enable power optimization such as power-aware compiler, core mapping, and scheduling techniques. Each component of the router is modeled by different methods according to different characteristics. Multiple linear regression is used to model the relationship between events occurring in the NoC and energy consumption. Using the EDA platform of Synopsys and SMIC 180nm standard cell library, we compare our power model to the gate-level power analysis by PrimeTime PX. Experimental results show that the average estimation error of the proposed power model is 5.0% against the gate-level simulation with 600 times speed up. © 2012 Springer-Verlag GmbH.