Challenges to Dependable Asynchronous Processor Design

Abstract

With a surprisingly rapid progress in device technology, high-speed logic gates with a switching delay of only a few picoseconds have been already reported to be available. Due to the fundamental limitation that no signal can reach further than 0.3 mm in 1 picosecond, the use of these extremely fast switching devices brings into the synchronous system design serious timing probles, i.e.wire delay and clock skew[1]. The global clock cannot be distributed over the entire region of a synchronous system at such a high frequency that stands comparison with the device speed. The basic performance of a synchronous system depends on the global clock frequency. While many efforts are being made to optimize the clock skew in VLSI processor design[2], there exists an obvious limitation which synchronous processor designs have already reached or will reach very soon in the performance enhancement. A preliminary performance estimation shows that a synchronous processor must be implemented on a square region with a size of less than 0.1mm x 0.1mm in order to fully enjoy the ultra-high speed of the “picosecond devices” [3].