Abstract
The fixed-size processor array architecture, which is intended for realization of matrix LL T -decomposition based on Cholesky algorithm, is proposed. In order to implement this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. The AU is intended for configuring in the Xilinx Virtex4 FPGAs, and its hardware complexity is much less than the complexity of similar AUs operating with floating-point numbers. © 2008 Springer-Verlag Berlin Heidelberg.
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CITATION STYLE
Maslennikow, O., Lepekha, V., Sergiyenko, A., Tomas, A., & Wyrzykowski, R. (2008). Parallel implementation of Cholesky LL T -Algorithm in FPGA-based processor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4967 LNCS, pp. 137–147). https://doi.org/10.1007/978-3-540-68111-3_15
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