Linearity Analysis of Line Tunneling Based TFET for High-Performance RF Applications

Abstract

In this work, in-line tunneling based dual metal double gate tunnel FET (DMDG-VTFET) is reported. A silicon epitaxial layer is present between the source and gate so as to align the carrier tunneling parallelly to the gate electric field. This proposed modulation in the design due to the introduction of silicon layer suppresses the parasitic tunneling paths which cause the depreciation of the subthreshold slope (SS). So, with this proposed device, a super-steep SS is achieved. The device parameters which are critical to the device characteristics are optimized such that the high-performance ON state current of 1.2 mA, low OFF state current nearly 3.53 fA and SS of 37 mV/decade are obtained. The reduction in SS of the device creates more room for the device scaling and makes it suitable for low-power and high switching speed applications. The accurate analysis of linearity of the device is also important hence linearity estimation of the device is done by investigating the linearity figures of merit such as VIP3, IMD3, IIP3, 1-dB compression point along with the temperature sensitivity analysis to get insight into the stability of the device in varying temperature environment.