Coarse Grain Reconfigurable Architectures(CGRA) support Spatial and Temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. We extend Edge-Betweenness Centrality scheme, originally used for detecting community structures in social and biological networks, for partitioning instructions of a dataflow graph. Comparisons of execution time for several applications run on a simulator for REDEFINE, a CGRA proposed in literature, indicate that Centrality scheme outperforms several other schemes with 2-18% execution time speedup. © 2011 Springer-Verlag.
CITATION STYLE
Krishnamoorthy, R., Varadarajan, K., Fujita, M., Alle, M., Nandy, S. K., & Narayan, R. (2011). Dataflow graph partitioning for optimal spatio-temporal computation on a coarse grain reconfigurable architecture. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6578 LNCS, pp. 125–132). https://doi.org/10.1007/978-3-642-19475-7_15
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