A comparison of performance between double-gate and gate-all-around nanowire mosfet

Abstract

Due to the rapid scaling of Complementary Metal-Oxide-Semiconductor (CMOS), the structure of the planar MOSFET approaches the scaling limits when the short channel effects (SCEs) become the main problem. The Double-Gate and Gate-all-Around nanowire MOSFETs are said to be the promising candidate to replace the planar MOSFET in order to pursue CMOS scaling. Therefore, this paper present the result of device simulation using Silvaco TCAD tools for Double-Gate and Gate-All-Around nanowire MOSFETs. The purpose of this simulation work is to compare the performance of GAA nanowire and DG MOSFET and then study the effect of physical parameter on electrical behavior for both devices. The result of the simulated model of Gate-All-Around nanowire is compared with published data. It was found that when the gate length of DG was scaled from 80nm to 10nm, the subthreshold slope is increasing from 62mV/dec to 162.7mV/dec. While for GAA, the subthreshold slope is increasing from 65.8mV/dec to 127mV/dec. The threshold voltage in DG and GAA at Lg=80nm are 0.40646V and-0.17505V respectively. Even though heavy doping was good for suppressing SCE, the lower doping concentration is desirable as the DG and GAA nanowire had higher on-state currents with 1.42x10-3A and 3.23x10-4A respectively. It also showed that the threshold voltage of DG and GAA nanowire increase from-0.0734V to 0.2312V and-0.0319V to 0.2232V respectively when the channel doping is varies from lower to higher concentration.