The newly introduced Microprocessor Architecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The first implementation, MAJC-5200, includes some ky features of MAJC to realize a high performance multimedia processor. Two CPUs running at 500 MHz are integrated into the chip to provide 6.16 GFLOPS and 12.33 COPS with high speed interfaces providing a peak input-output (I/O) data rate of more than 4.8 G Bytes/second. The c hip is suitable for a number of applications including graphics/multimedia processing for high-end set-top boxes, digital voice processing for telecommunications, and advanced imaging. ?© 2000 Springer-Verlag Berlin Heidelberg.
CITATION STYLE
Sudharsanan, S. (2000). MAJC-5200: A high performance microprocessor for multimedia computing. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1800 LNCS, pp. 163–170). Springer Verlag. https://doi.org/10.1007/3-540-45591-4_22
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