Integrating SMT with theorem proving for analog/mixed-signal circuit verification

Abstract

We present our integration of the Z3 SMT solver into the ACL2 theorem prover and its application to formal verification of analogmixed signal circuits by proving global convergence for a state-of-theart digital phase-locked loop (PLL). SMT (satisfiability modulo theory) solvers eliminate much of the tedium associated with detailed proofs by providing automatic reasoning about propositional formulas including equalities and inequalities of polynomial functions. A theorem prover complements the SMT solver by providing a proof structuring and proof by induction. We use this combined tool to show global convergence (i.e. correct start-up and mode-switching) of a digital PLL. The PLL is an example of a second-order hybrid control system; its verification demonstrates how these methods can address challenges that arise when verifying such designs.