Partial run-time reconfiguration using JRTR

Abstract

Much has been written about the design and performance advantages of partial Run-Time Reconfiguration (RTR) over the last decade. While the results have been promising, commercial support for partial RTR has lagged. Until the introduction of the Xilinx Virtex(tm) family of devices, no mainstream, commercial FPGA has provided support for this capability. In this paper we describe JRTR, a software package which provides direct support for partial run-time reconfiguration. Using a cache-based model, this implementation provides fast, simple support for partial run-time reconfiguration. While the current implementation is on the Xilinx Virtex family of devices using the JBits tool suite, this approach may be applied to any SRAM-based FPGA that provides basic support for RTR.