Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Abstract

Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.