Design of Energy Efficient ALU Using Clock Gating for a Sensor Node

Abstract

Recent growth in the need of fast devices and complex designs on a single System on Chip (SoC) mainly requires a low power and a highly efficient design in terms of speed and area. Moreover the Wireless Sensor Nodes which performs on the node processing are mainly powered by battery thereby requiring the processing element to consume less power for computations. The two ways of reducing power consumption is by either reducing static power consumption or by reducing dynamic power consumption. This paper has concentrated on reducing the dynamic power consumption using clock gating scheme. This scheme is applied to a 16-bit Arithmetic and Logic Unit with two distinct approaches namely Block Enabled Clock Gating and Functional Unit Enabled Clock Gating. A Comparative analysis is done for ALU without and with two distinct clock gating schemes. The reduction in clock power and dynamic power consumption is achieved with higher frequencies. Simulations and power analysis is done using Xilinx Vivado Simulator. With Functional unit enabled clock gating we could get more than 70% reduction in power for higher frequencies like 1 and 2 GHz.