GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications

Abstract

III-V semiconductors present interesting properties and are already used in electronics, lightening and photonic devices. Integration of III-V devices onto a Si CMOS platform is already in production using III-V devices transfer. A promising way consists in using hetero-epitaxy processes to grow the III-V materials directly on Si and at the right place. To reach this objective, some challenges still needed to be overcome. In this contribution, we will show how to overcome the different challenges associated to the heteroepitaxy and integration of III-As onto a silicon platform. We present solutions to get rid of antiphase domains for GaAs grown on exact Si(100). To reduce the threading dislocations density, efficient ways based on either insertion of InGaAs/GaAs multilayers defect filter layers or selective epitaxy in cavities are implemented. All these solutions allows fabricating electrically pumped laser structures based on InAs quantum dots active region, required for photonic and sensing applications. 1. Part 1: GaAs growth on Si(001) The growth of polar zinc-blende GaAs on a non-polar Si(001) substrate can lead to planar defects named antiphase boundary (APB). The APB planes are made of III-III or/and V-V bonds that can propagate in the layer through the {110}, {111} or higher index planes (Figure 1) [2, 3]. The elastic strain field due to APB changes atomic distances and hence electronic states, acts as a carrier diffusion and/or non-radiative recombination centers. APBs nucleate at the edges of the single-layer steps present at nominal (001) silicon surfaces. Until now, the APBs formation was mainly inhibited by using (i) off-axis Si(001) substrates tilted by 4-6° towards [110] direction [4, 5] or (ii) Si(211) sub-strates [6] where Si double-layer steps could be formed easily. However, these wafers are not compatible with industrial Si CMOS standards which uses nominal Si (001) wafers, i.e. with a miscut angle equal or lower than 0.5°. The best option to prevent the APBs nucleation is to promote double layer step formation on nominal Si(001) substrate as it is the case for off-axis wafers.