Study of Efficient FIR Filter Architecture for Fixed and Reconfigurable Applications

Abstract

Transpose type Finite-Impulse Response (FIR) filters are implicitly pipelined and endorse the technique of Multifold Constant Multiplications (MCM). The studied model explores the possibility of understanding block FIR filters in the transpose form pattern for the efficient realization of broad order FIR filters for both fixed and reconfigurable applications in area-delay. A flow graph optimized registry complexity is built based on the computational study of transpose type configuration of the FIR filter. The proposed translate type block filter is an architecture based on a multiplier. Analysis is done towards the need of an optimum low complexity design using the MCM model for the block realization of fixed FIR filters. Since power dissipation is directly linked to the hardware, the use of MCM algorithms indirectly achieves a certain amount of power reduction. MCM is therefore largely found to be sufficient for the implementation of Broad Order design research. Using Data Flow Graph, which has been comprehensively iterated based on the ability to execute algorithms and their enhancement with a high degree of parallel and asynchronous operation, the computation process in MCM is likely to be well performed.