ECC memory for fault tolerant risc-v processors

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Abstract

Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed.

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Dörflinger, A., Guan, Y., Michalik, S., Michalik, S., Naghmouchi, J., & Michalik, H. (2020). ECC memory for fault tolerant risc-v processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 12155 LNCS, pp. 44–55). Springer. https://doi.org/10.1007/978-3-030-52794-5_4

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