Designing and modeling mpsoc processors and communication architectures

Abstract

In this chapter, the mapping of the MESCAL methodology onto the CoWare tool suite is discussed. In order to understand the mapping it is helpful to first understand the key ideas and properties of the tools. First of all, the CoWare tools address both issues of designing and programming a platform: The design of the computational elements as well as their interconnects. The embedded processor designer (LISATek™) allows the user to jointly design the architecture of an ASIP and the software development tools. In LISATek the ASIP is captured by a single model from which the tools (Ccompiler, assembler, linker, instruction-set simulator, etc.) and the RTL hardware implementation are generated automatically, thus allowing an iterative design process to evaluate architectural alternatives. The early consideration of C-compiler requirements to the architecture guarantees the successful deployment of the architecture. LISATek offers the designer the full architectural design space. The possibilities range from designing a simple computational element with only a very few instructions to using advanced architectural concepts such as VLIW, SIMD, etc. in a complex processor. Thus, the designer has the possibility to optimally match the architecture to the requirements. From an economical standpoint designing an in-house processor is a very attractive proposition since the IP is fully protected and costly license fees and royalties are eliminated. The tool suite can be viewed as a workbench which separates the automatic generation of tools from optimization tasks. For example, in the implementation path the designer has the option to employ various optimization techniques on top of logic synthesis. Another example is instruction set synthesis. This open architecture allows the designer to incorporate innovative optimization strategies when they become available. This is of key importance as the optimization of ASIPs is a very active area of research. The interconnect of the processing elements (ASIP) of a platform is as important as the elements themselves. As the traditional bus structures do not meet future on-chip communication requirements, the trend is towards fully network-on-chip (NoC) concepts. A tool suite must be capable to model these networks at various abstraction levels, both temporal and spatial. The philosophy underlying the CoWare tool suite (convergensc™) employs the principle of orthogonalization of concerns [126]. Analogously as in telecommunication networks, the communication services are offered independently of the actual network topology. This allows the designer of a platform to explore network alternatives. For example, it allows the designer to trade computation versus communication ("the network is the computer"). So far we have discussed the two tool boxes to design and program platforms individually. As has been emphasized throughout in the introduction of this book the two elements must work seamlessly together in order to be useful in practice (see element 5: The successful deployment). This is of utmost importance for the actual user of the platform: The application programmer. He needs access to a virtual platform long before silicon is out, as discussed later on in the chapter. © 2005 Springer Science+Business Media, Inc.