This paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques. © Springer-Verlag Berlin Heidelberg 2006.
CITATION STYLE
Kim, D. H., & Lee, H. J. (2006). Integrated Instruction Scheduling and fine-grain Register allocation for embedded processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4017 LNCS, pp. 269–278). Springer Verlag. https://doi.org/10.1007/11796435_28
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