CMOS PLL Design in a Digital Chip Environment

Abstract

CMOS PLL's are becoming increasingly useful for clock synthesis and recovery in CPU and other digital chip designs. However, the packaging and process are defined to meet the requirements of the digital chip, not the analog portions of the PLL. The environment defined by the digital requirements includes the package, the process and the dominant noise source. Packages for complex digital chips are larger and have more complex frequency and signal integrity characteristics than smaller packages that are appropriate for dedicated analog chips. Digital CMOS processes lack the quality capacitors, resistors and possible variety of devices that may be found in a process developed specifically for analog purposes. Digital switching causes significant noise that dominates the spectrum that the circuit designer must worry about. This paper considers a typical CMOS PLL design from the digital chip design viewpoint.