An O(n log n) algorithm for 1-D tile compaction

Abstract

A puzzle whose solution has applications in VLSI layout compaction of memories and fine grained parallel processors can be phrased as follows: You are given a set of n rectangles arranged in a coordinate plane such that no two overlap and each rectangle has sides parallel to the coordinate axes. The width of such an arrangement is the length of a longest horizontal line segment having each of its endpoints located within the rectangles. You may slide the rectangles only in the direction of the horizontal axis and may not slide any rectangle over another. Find a minimal width arrangement reachable by sliding from the original arrangement. The fastest previously known algorithm solving this problem is the iterative approach of Mehlhorn and Rülling [6] requiring O(n2log n) time. This paper develops and proves correct a simple O(n log n) time algorithm which exploits the geometric structure of the constraints between the rectangles.