Abstract
We present a hardware mechanism which dynamically detects uniform and affine vectors used in SPMD architecture such as Graphics Processing Units, to minimize pressure on the register file and reduce power consumption with minimal architectural modifications. A preliminary experimental analysis conducted with the Barra simulator shows that this optimization can benefit up to 34 % of register file reads and 22 % of the computations in common GPGPU applications. © 2010 Springer-Verlag.
Cite
CITATION STYLE
Collange, S., Defour, D., & Zhang, Y. (2010). Dynamic detection of uniform and affine vectors in GPGPU computations. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6043 LNCS, pp. 46–55). https://doi.org/10.1007/978-3-642-14122-5_8
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