What’s in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components

Abstract

Many large scale circuits and systems contain a mixture of synchronous and asynchronous (self-timed) subsystems; examples include digital control units and sequencers, processing units that have asynchronous interfaces to busses or memories, and systems that contain modules that are clocked by independent, locally generated clocks. This paper addresses some of the formal issues that arise in the specification and synthesis of such “mixed-mode” systems. In particular, we outline a specification technique suitable for such systems, formalize the notion of timing disciplines in this context, and indicated how the introduction of timing disciplines into a design affect the associated specifications. We also outline the correlations between the semantic models underlying such specifications, called temporally annotated labeled event structures (abbreviated TALES) and timing diagrams that are commonly used for specifying some of the temporal characteristics of interfaces. Some experiments in prototyping some of the implementation strategies for asynchronous, self-timed and mixed-mode systems are summarized.