This chapter discusses the problem of malicious hardware, or gateware, on FPGAs. Categories of malicious hardware, the problem of foundry trust, and attacks facilitated by malicious inclusions are presented. This chapter also explains the problem of covert channels on FPGAs, with a formal definition of a covert channel in general and a description of the specific case of covert channels on FPGAs. Methods for detecting and mitigating these covert channels are also described.
CITATION STYLE
Huffmire, T., Irvine, C., Nguyen, T. D., Levin, T., Kastner, R., & Sherwood, T. (2010). Hardware Security Challenges. In Handbook of FPGA Design Security (pp. 71–85). Springer Netherlands. https://doi.org/10.1007/978-90-481-9157-4_3
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