Voltage THD limits for three- and single-phase multilevel inverters

Abstract

This paper deals with single and three phase multilevel inverters power quality. The voltage total harmonic distortion rate is an important criterion for choosing the number of inverter levels and checking compatibility with power quality requirements. In this study, the author raises an interesting issue related to the definition of voltage THD boundaries with upper and lower limits. The problem is reformulated, and a novel and more practical approach is developed for three- and single-phase multilevel inverters. Found upper and lower voltage THD limits are sufficiently verified with most known switching algorithms like sinusoidal modulation (SM) with phase disposition (PD), space vector modulation (SVM) and selective harmonic elimination (SHE). They are also valid for cascaded (H-Bridge), neutral point clamped (NPC) and flying capacitors (FC) multilevel inverters.